Recently, as a next-generation NVRAM (Nonvolatile Random Access Memory) capable of implementing high-speed action to be replaced with a flash memory, various kinds of device structures such as a FeRAM (Ferroelectric RAM), a MRAM (Magnetic RAM), and an OUM (Ovonic Unified Memory) have been competitively developed in view of implementing high performance, high reliability, low cost, and process consistency.
In addition, based on these existing technique, a method of changing electric resistance reversely by applying an electric pulse to the perovskite material known for a super colossal magnetoresistance effect is disclosed by Shangquing Liu, Alex Ignatiev et al. in University of Houston, in the following patent document 1 and non-patent document 1. This is extremely innovative because resistance change over several digits can be implemented at a room temperature without applying an electric field while using the perovskite material known for the super colossal magnetoresistance effect. A resistance nonvolatile RRAM (Resistance Random Access Memory) using a variable resistance element and employing this phenomenon is extremely low in power consumption because it does not need a magnetic field at all unlike the MRAM and easy to miniaturize and highly integrate and has a considerably large dynamic range of the resistance change as compared with the MRAM, so that it has excellent characteristics such that multilevel storage can be implemented. The basic structure in an actual device is considerably simple such that a lower electrode material, a provskite-type metal oxide, and an upper electrode material are laminated in this order on a substrate in the vertical direction. In addition, according to the element structure illustrated in patent document 1, the lower electrode material is yttrium-barium-copper oxide YBa2Cu3O7 (YBCO) film deposited on a single-crystal substrate of lanthanum-aluminum oxide LaAlO3 (LAO), the perovskite-type metal oxide is a crystalline praseodymium-calcium-manganese oxide Pr1-xCaxMnO3 (PCMO) film, and the upper electrode material is an Ag film deposited by sputtering. According to the action of the memory element, it is reported that the resistance can be reversibly changed by applying positive and negative voltage pulse of 51 volts between the upper and lower electrodes. The novel nonvolatile semiconductor memory device is implemented by reading the resistance value in this reversible resistance changing action (referred to as the “switching action” occasionally hereinafter).
A nonvolatile semiconductor memory device is constituted such that a memory cell array in which memory cells comprising a variable resistance element consisting of the PCMO film and the like and storing information by the change of the electric resistance of the variable resistance element are arranged in a row direction and column direction like a matrix is formed, and circuits for controlling data programming, erasing and reading for each memory cell in the memory cell array are disposed around the memory cell array.
As the constitution of the memory cell comprising the variable resistance element, a two-terminal memory cell comprising only the variable resistance element is called a 1R type memory cell.
FIG. 1 shows one constitution example of a large-capacity nonvolatile semiconductor memory device in which a memory cell array 1 has 1R type memory cells as components. As shown in FIG. 2, a 1R type memory cell 10 comprises a single variable resistance element and the memory cells 10 are arranged in a matrix shape to constitute the memory cell array 1, which is similar to that disclosed in the following patent document 2, for example. More specifically, the memory cell array 1 is constituted such that m×n memory cells 10 are disposed at intersections of m (BL1 to BLm) bit lines extending in the column direction and n (WL1 to WLn) word lines extending in the row direction. According to each memory cell 10, the upper electrode of the variable resistance element is connected to the word line, and the lower electrode of the variable resistance element is connected to the bit line. In addition, the relation between the upper electrode and the lower electrode of the variable resistance element may be reversed such that the lower electrode of the variable resistance element is connected to the word line and the upper electrode of the variable resistance element is connected to the bit line.
As shown in FIG. 1, according to the nonvolatile semiconductor memory device comprising the memory cell array 1 comprising the 1R type memory cells 10, a specific memory cell in the memory cell array 1 corresponding to an address input inputted to a control circuit 6a from an address line 4 is selected by a bit line decoder 2 and a word line decoder 3, and each action of data programming, erasing and reading is carried out so that data is stored in the selected memory cell and read. The data input/output with an external device (not shown) is performed through a data line 5.
The word line decoder 3 selects the word line of the memory cell array 1 according to a signal inputted to the address line 4. The bit line decoder 2 selects the bit line of the memory cell array 1 according to an address signal inputted to the address line 4. The control circuit 6a controls each action of data programming, erasing and reading of the memory cell array 1. The control circuit 6a controls the word line decoder 3, the bit line decoder 2, a voltage switch circuit 8a, and programming, erasing and reading action of the memory cell array 1, based on the address signal inputted from the address line 4, a data input (at the time of programming) inputted from a data line 5, and a control input signal inputted from a control signal line 7. In the example shown in FIG. 1, the control circuit 6a is provided with a function as a general address buffer circuit, data input/output buffer circuit, and control input buffer circuit though they are not shown.
The voltage switch circuit 8a switches each voltage of the word line and bit line required for the reading action, programming action and erasing action of the memory cell array 1 according to an action mode and supplies it to the memory cell array 1. Here, reference character Vcc designates a power supply voltage of the nonvolatile semiconductor memory device of the present invention, reference character Vss designates the ground voltage, reference character Vpp designates a programming or erasing voltage, and reference character V1 designates a reading voltage. In addition, the data reading is carried out from the memory cell array 1 through the bit line decoder 2 and the reading circuit 9. The reading circuit 9 determines the state of the data and transfers its result to the control circuit 6a to be outputted to the data line 5.
In the memory cell array 1 comprising the 1R type memory cells 10, a reading current flowing in the memory cell selected by the row or column is detected as the reading current of the memory cell to be read. Although the reading current flows in other memory cells of the memory cell array 1 comprising the 1R type memory cells 10, there are advantages that the memory cell structure is simple and the memory cell area and memory cell array area are small.
A conventional example of an electric pulse applying process to each part in the memory cell array 1 comprising the 1R type memory cells 10 at the time of data reading action will be described with reference to FIGS. 2 and 3. When the data in the selected memory cell is read, the selected word line connected to the selected memory cell is kept at Vss and the reading voltage V1 is applied to unselected word lines and all the bit lines during a reading period Tr. During the reading period Tr, since the voltage difference of the reading voltage V1 is generated between the selected word line and all the bit lines, a reading current corresponding to its electric resistance, that is, the memory state flows in the variable resistance element of the selected memory cell, so that the data stored in the selected memory cell can be read. In this case, since the reading current corresponding to the memory state of the selected memory cell connected to the selected word line flows in each bit line, when the reading current flowing in a certain selected bit line is selectively read on the bit line side, the data in the specific selected memory cell can be read. Here, the relation of the bit line and the word line may be switched such that the reading current flowing in each word line is selectively read on the word line side.
FIG. 5 shows a conventional example of an electric pulse applying method to each word line and each bit line at the time of data reading, programming or erasing action in the memory cell array 1 comprising the 1R type memory cells 10, and FIG. 4 shows one example of a nonvolatile semiconductor memory device for controlling it. The example of the electric pulse applying method to each word line and each bit line shown in FIG. 5 is similar to that disclosed in a non-patent document 2. When data is read, programmed or erased in the selected memory cell, the ground voltage Vss is applied to one of the selected word line and the selected bit line connected to the selected memory cell and a voltage Va required for implementing the reading action, programming action or erasing action is applied to the other of the selected word line or the selected bit line. The voltage of all unselected word lines and all unselected bit lines is set to the half of the voltage Va required for implementing the reading, programming or erasing action, that is, Va/2.
The nonvolatile semiconductor memory device having the constitution shown in FIG. 4 is basically the same as that of the conventional nonvolatile semiconductor memory device shown in FIG. 1. It is different from the conventional non-volatile semiconductor memory device shown in FIG. 1 in the voltage supplied from the voltage switch circuit 8b to each word line and each bit line of the memory cell array 1 and a control method of that voltage. According to the constitution shown in FIG. 4, the voltage switch circuit 8b applies the voltages Va and Va/2 to a certain bit line and word line in addition to the voltage Vcc and Vss.
FIG. 7 shows another conventional example of an electric pulse applying method to each word line and each bit line at the time of data reading, programming or erasing action in a memory cell array 1 comprising 1R type memory cells 10, and FIG. 6 shows one example of a nonvolatile semiconductor memory device for controlling it. The example of the electric pulse applying method to each word line and each bit line shown in FIG. 7 is similar to that disclosed in the non-patent document 2. When data is read, programmed or erased for the selected memory cell, the ground voltage Vss is applied to one of the selected word line and the selected bit line connected to the selected memory cell and a voltage Va required for implementing the reading action, programming action or erasing action is applied to the other of the selected word line or the selected bit line. A voltage of two thirds of the voltage Va required for the reading, programming or erasing action, that is, 2Va/3 is applied to all unselected lines on the side to which the ground voltage Vss is applied, among the word lines and bit lines. A voltage of one third of the voltage Va, that is, Va/3 is applied to all unselected lines on the side to which the voltage Va is applied, among the word lines and bit lines.
The nonvolatile semiconductor memory device having the constitution shown in FIG. 6 is basically the same as that of the conventional nonvolatile semiconductor memory device shown in FIG. 1. It is different from the conventional non-volatile semiconductor memory device shown in FIG. 1 in the voltage supplied from a voltage switch circuit 8c to each word line and each bit line of the memory cell array 1 and a control method of that voltage. According to the constitution shown in FIG. 6, the voltage switch circuit 8c applies the voltages Va, 2Va/3 and Va/3 to a certain bit line and word line in addition to the voltages Vcc and Vss.
The variable resistance element constituting the 1R type memory cell includes a phase-change memory element in which a resistance value is changed by the change in crystalline/amorphous state of chalcogenide compound, a MRAM element using a resistance change by a tunnel magnetic resistance effect, a memory element of a polymer ferroelectric RAM (PERAM) in which a resistance element is formed of a conductive polymer, a RRAM element causing a resistance change by an electric pulse application and the like.    Patent document 1: U.S. Pat. No. 6,204,139    Patent document 2: Japanese Unexamined Patent Publication No. 2002-8369    Non-patent document 1: Liu, S. Q. et al. “Electric-pulse-induced reversible Resistance change effect in magnetoresistive films”, Applied Physics Letter, Vol. 76, pp. 2749-2751, in 2000.